The AT91 I2C HPL interface. See pages 287-303 in the At91SAM7S Series Preliminary
val
- :
AT91C_TWI_TXCOMP - Transmission completed
AT91C_TWI_RXRDY - Receive holding register ready
AT91C_TWI_TXDRY - Transmit holding register ready
AT91C_TWI_NACK - Not acknowledged
AT91C_TWI_OVRE - Overrun Error
AT91C_TWI_UNRE - Underrun Error
val
- :
AT91C_TWI_START - Send a start condition
AT91C_TWI_STOP - Send a stop condition
AT91C_TWI_MSEN - Master transfer enabled
AT91C_TWI_MSDIS - Master Transfer disabled
AT91C_TWI_SWRST - Software reset
val
- :
AT91C_TWI_CLDIV - Clock low divider
AT91C_TWI_CHDIV - Clock high divider
AT91C_TWI_CKDIV - Clock divider
val
- :
AT91C_TWI_TXCOMP - Transmission completed
AT91C_TWI_RXRDY - Receive holding register ready
AT91C_TWI_TXRDY - Transmit holding register ready
AT91C_TWI_NACK - Not acknowledge
val
- :
AT91C_TWI_TXCOMP - Transmission completed
AT91C_TWI_RXRDY - Receive holding register ready
AT91C_TWI_TXRDY - Transmit holding register ready
AT91C_TWI_NACK - Not acknowledge
val
- :
AT91C_TWI_DADR - Device address
AT91C_TWI_MREAD - Master read direction
AT91C_TWI_IADRSZ - Internal Device Address (0 means no internal device addr.)
val
- The byte to transmit in bit 7:0.